`include "defines.v"

module if_id(
    //from ctrl
    input wire[`Hold_Flag_Bus] hold_flag_i,

    input wire clk,
    input wire rst,
    //from if_
    input wire[`InstBus] Inst_i,
    input wire[`InstAddrBus] InstAddr_i,
    //to id
    output reg[`InstBus] Inst_o,
    output reg[`InstAddrBus] InstAddr_o
);

always @(posedge clk)
    begin
        if (rst == `RstEnable)
            begin
                Inst_o = `ZeroWord;
                InstAddr_o = `ZeroWord;
            end
        else if (hold_flag_i >= `Hold_If)
            begin
                Inst_o = `INST_NOP;
                InstAddr_o = InstAddr_i;
            end
        else
            begin
                Inst_o = Inst_i;
                InstAddr_o = InstAddr_i;
            end
    end



endmodule